Dynamic random access memory circuits (DRAMs) are "dynamic" in the sense that the stored data, typically in the form of charged and discharged capacitors or memory cells arranged in a large array, will dissipate after a relatively short period of time. Thus, in order to retain the information, the contents of the DRAM must be refreshed; that is, the charged or discharged state of the capacitor must be reapplied to each individual memory cell in a repetitive manner. The maximum amount of time allowable between refreshing operations is determined by the charge storage capabilities of the capacitors that make up the memory cell array. The memory circuit manufacturer typically specifies a refresh time for which it guarantees data retention in the memory cells.
Memory cell arrays are typically arranged in rows and columns such that a particular memory cell may be addressed by specifying its row and column within the array. A wordline connects a row of cells to a set of sense amplifiers that detect the data in the cells. In a read operation a subset of the data in the sense amplifiers is then chosen, or "y-selected." for output. A refresh operation is similar to a read operation, but no data is output. The sensing of the data in the cells by the sense amplifiers simultaneously results in the data being rewritten to the cells. The data is thus "refreshed".
Several refresh schemes are in common use and many DRAMs include several refresh options to be chosen by the user. For example, in the RAS-only refresh mode, the timing of the refresh and the addresses of the cells to be addressed are provided from a source external to the memory circuit, from a processor or memory controller, for example. In the CAS.sub.-- before RAS.sub.-- (CBR) refresh mode, it is typical that during normal memory system operations the memory circuit receives refresh control inputs from a processor or other application-specific integrated circuit such as a memory controller, but the addresses of the rows to be refreshed are generated by a counter internal to the integrated circuit. The DRAM typically enters CBR refresh mode when a control input signal called the column address strobe (CAS) transitions from one logic state to another before and within a specified time period of when the row address strobe (RAS) is taken from one logic state to another. Thus, the timing of the refresh is governed by external inputs (through RAS and CAS), but the addressing operations are governed by an on-chip counter. In CBR and RAS-only refresh modes, refresh is usually accomplished by sequentially accessing all of the rows in the array. As mentioned above, by simply accessing the rows, the data contained in the rows of cells is refreshed. In the process of detecting a datum in a cell, that datum is written back into the cell at the rail voltages, typically 0 Volts and 3.3 Volts.
In periods such as a system standby or "sleep" mode when CAS.sub.--, RAS.sub.--, and other control signals from a processor or memory controller are inactive, DRAMs are often designed to revert to a self-refresh mode in which the refresh operations are controlled by the DRAM itself without external control inputs. Such a self-refresh mode is described in U.S. Pat. No. 5,365,487 issued to Patel, Brown, and Tso. This mode allows a computer system user, for example, to avoid storing data to disk and turning off the computer to save power. The self-refresh mode of the memory circuit is designed to consume as little refresh power as possible.
The foregoing has been addressed to DRAMs in general. Note also that synchronous DRAMs have analogous refresh modes to those described above. The mode analogous to the RAS-only refresh mode of a DRAM is an Activate-Deactivate cycle (ACT-DEAC/DCAB). DEAC deactivates or precharges a specified bank depending upon the Bank-select address during DEAC-command entry, while DCAB deactivates all of the banks and is typically implemented with a DEAC command along with a particular address pin being held high. The CBR-refresh analogy in synchronous memories is called Auto-refresh. Both the auto-refresh and self-refresh modes in an SDRAM are implemented with specific commands rather than with the usual CAS-before-RAS sequence used in an asynchronous DRAM.
In the traditional CBR refresh, all of the rows within the memory array (4096 rows are typical in 16 Mb and 64 Mb devices) are accessed sequentially within the refresh period specified by the manufacturer. The normal memory operations of read and write are accomplished during rest periods in refresh operations. Thus, the CBR refresh mode, which relies on external control signals for the timing of the refresh, is typically used when the DRAM is likely to be accessed by a processor or memory controller, for example. In contrast, in the sleep mode of a computer system for example, no external control inputs are provided by a processor or memory controller, so the DRAM is free to allocate the refresh cycles within the refresh period to maximize efficiency, power management, and so forth. It is common for twice as many rows or wordlines to be refreshed at a time during self-refresh mode, thus halving the number of cycles or row accesses required to refresh the entire array. For example, the complete array may be refreshed in only 2048 cycles, rather than the 4096 required to refresh the rows one at a time.
A typical 64 megabit DRAM, for example, may require addressing all wordlines at 4096 addresses every 64 ms in CBR mode. The average time between each refresh address. therefore, is about 16 .mu.s. The same DRAM may alternatively refresh itself by an internal counter designed to refresh twice as many wordlines each cycle at only 2048 addresses. The internal counter operates at a lower frequency than CBR mode refresh to conserve power, but it must refresh all wordlines in 160 ms to avoid data loss. Thus, an average self-refresh cycle time is 80 .mu.s. A problem arises at low counter frequencies during a transition from self-refresh mode to CBR refresh mode. When the DRAM exits self-refresh mode, two wordlines are due to be refreshed within 80 .mu.s. Normal CBR refresh, however, would require 2048 of 4096 refresh cycles or 32 ms to refresh both wordlines. This greatly exceeds the 80 us refresh requirement for one of the wordlines. Increasing the self-refresh counter frequency would provide more time to refresh both wordlines, but this would increase power consumption. Alternatively, a requirement to increase the CBR refresh frequency upon self-refresh exit would impose an additional burden on the memory system.